`include "common.svh"

module compress_issue_queue_test #(
    parameter RF_WRITE_WIDTH = 5,
    parameter ENQ_WIDTH = 4,
    parameter DEQ_WIDTH = 1,
    parameter SIZE = 16
) (

    input clk,
    input rst,
    //Redirect
    // input i_redirect_valid,
    // input ROB_PTR i_redirect_rob_idx,
    //from regfile write port
    input i_write_valid[RF_WRITE_WIDTH-1:0],
    input PRF_IDX i_write_prf_idx[RF_WRITE_WIDTH-1:0],
    input word_t i_write_prf_data[RF_WRITE_WIDTH-1:0],
    //from dispatch
    input i_valid[ENQ_WIDTH-1:0],
    // input ISSUE_OP i_iop[ENQ_WIDTH-1:0],
    input ROB_PTR i_iop_rob_idx[ENQ_WIDTH-1:0],
    input PRF_IDX i_iop_prs1[ENQ_WIDTH-1:0],
    input PRF_IDX i_iop_prs2[ENQ_WIDTH-1:0],
    input word_t i_iop_src1[ENQ_WIDTH-1:0],
    input word_t i_iop_src2[ENQ_WIDTH-1:0],
    input i_iop_src1_valid[ENQ_WIDTH-1:0],
    input i_iop_src2_valid[ENQ_WIDTH-1:0],
    output i_ready,
    //to exu
    output o_valid[DEQ_WIDTH-1:0],
    output RenamedOP o_iop_rop[DEQ_WIDTH-1:0],
    output ROB_PTR o_iop_rob_idx[DEQ_WIDTH-1:0],
    output PRF_IDX o_iop_prs1[DEQ_WIDTH-1:0],
    output PRF_IDX o_iop_prs2[DEQ_WIDTH-1:0],
    output word_t o_iop_src1[DEQ_WIDTH-1:0],
    output word_t o_iop_src2[DEQ_WIDTH-1:0],
    output o_iop_src1_valid[DEQ_WIDTH-1:0],
    output o_iop_src2_valid[DEQ_WIDTH-1:0],
    input o_ready
);
  ISSUE_OP i_iop[ENQ_WIDTH-1:0];
  ISSUE_OP o_iop[DEQ_WIDTH-1:0];
  genvar gi;
  generate
    for (gi = 0; gi < ENQ_WIDTH; gi = gi + 1) begin : en_queue
      always_comb begin
        i_iop[gi].rop = 'b0;
        i_iop[gi].rop.prs1 = i_iop_prs1[gi];
        i_iop[gi].rop.prs2 = i_iop_prs2[gi];
      end
      // assign i_iop[gi].rop = 'b0;
      assign i_iop[gi].rob_idx = i_iop_rob_idx[gi];
      assign i_iop[gi].src1 = i_iop_src1[gi];
      assign i_iop[gi].src2 = i_iop_src2[gi];
      assign i_iop[gi].src1_valid = i_iop_src1_valid[gi];
      assign i_iop[gi].src2_valid = i_iop_src2_valid[gi];
    end
    for (gi = 0; gi < DEQ_WIDTH; gi = gi + 1) begin : de_queue
      assign o_iop_prs1[gi] = o_iop[gi].rop.prs1;
      assign o_iop_prs2[gi] = o_iop[gi].rop.prs2;
      assign o_iop_rop[gi] = o_iop[gi].rop;
      assign o_iop_rob_idx[gi] = o_iop[gi].rob_idx;
      assign o_iop_src1[gi] = o_iop[gi].src1;
      assign o_iop_src2[gi] = o_iop[gi].src2;
      assign o_iop_src1_valid[gi] = o_iop[gi].src1_valid;
      assign o_iop_src2_valid[gi] = o_iop[gi].src2_valid;
    end
  endgenerate
  compress_issue_queue #(RF_WRITE_WIDTH, ENQ_WIDTH, DEQ_WIDTH, SIZE) inst_compress_issue_queue (.*);
endmodule
